智慧視覺系統設計實驗室

Yu-Shu Ni, Wei-Lun Chen, Yi Liu, Ming-Hsuan Wu and Jiun-In Guo, “Optimizing Automated Optical Inspection: An Adaptive Fusion and Semi-Supervised Self-Learning Approach for Elevated Accuracy and Efficiency in Scenarios with Scarce Labeled Data,” Sensors 2024, 24(17), 5737; https://doi.org/10.3390/s24175737 (SCI, IF=3.847)

Vinay M. Shivanna, and Jiun-In Guo,” Object Detection, Recognition, and Tracking Algorithms for ADASs—A Study on Recent Trends,” Sensors 2024, 24(1), 249. https://doi.org/10.3390/s24010249 (SCI, IF=3.847)

Po-Hung Lin, Vinay M. Shivanna, Jiun-Shiung Chen, and Jiun-In Guo,” 360° Map Establishment and Real-Time Simultaneous Localization and Mapping Based on Equirectangular Projection for Autonomous Driving Vehicles,” Sensors 2023, 23(12), 5560. https://doi.org/10.3390/s23125560 (SCI, IF=3.847)

Jiun-In. Guo, “Feature People: Interview with Prof. Jiun-In Guo”, CTSoC-NCT News on Consumer Technology (NCT), February 2023 Issue, https://ctsoc.ieee.org/publications/ctsoc-nct.html, Feb. 2023.

Jia-Jheng Lin, Jiun-In Guo*, Vinay M. Shivanna, Ssu-Yuan Chang, “Deep Learning Derived Object Detection and Tracking Technology based on Sensor Fusion of Millimeter-wave Radar/Video and its Application on Embedded Systems,” Sensors 2023, 23(5), 2746; Special Issue "Single Sensor and Multi-Sensor Object Identification and Detection with Deep Learning", March 2^nd, 2023. https://www.mdpi.com/1424-8220/23/5/2746 (SCI, IF=3.847)

Bo-Xun Wu, Vinay M. Shivanna, Hsiang-Hsuan Hung, Jiun-In Guo,” ConcentrateNet: Multi-Scale Object Detection Model for Advanced Driving Assistance System Using Real-Time Distant Region Locating Technique,” Sensors 2022, 22, 7371. https://doi.org/10.3390/s22197371  (SCI, IF=3.847)

Hung-Wei Lin, Vinay M. Shivanna, Hsiu Chi Chang, and Jiun-In Guo,” Real-Time Multiple Pedestrian Tracking with Joint Detection and Embedding Deep Learning Model for Embedded Systems,” IEEE Access, May 9^th, 2022. (SCI, IF=3.476, H-index=127, JCI Rank=104/344 in Engineering, Electrical and Electronics) DOI: 10.1109/ACCESS.2022.3173408

Tzu-Hsien Sang, Kuan-Yu Tseng, Feng-Tsun Chien, Chia-Chih Chang, Yi-Hsin Peng, and Jiun-In Guo, “Deep Learning-based Velocity Estimation for FMCW Radar with Random Pulse Position Modulation,” IEEE Sensors Letters, Vol. 6, Issue 3, March 2022 (SCI, IF=2.36) DOI: 10.1109/LSENS.2022.3156882

Yu-Shu Ni, Vinay Malligere Shivanna, Jiun-In Guo,” iVS Dataset and ezLabel: A Dataset and a Data Annotation Tool for Deep Learning based ADAS Applications,” Remote Sensing, 2022, 14, 833. Feb. 10, 2022 (SCI, IF=5.349, H-index=144, JCI rank=65/324 in Environmental Science), https://doi.org/10.3390/rs14040833

Tzu-Hsien Sang, Feng-Tsun Chien, Chia-Chih Chang, Kuan-Yu Tseng, Bo-Sheng Wang, and Jiun-In Guo,” DoA Estimation for FMCW Radar by 3D-CNN,” Sensors, vol. 21, no. 16, Aug. 2021, (SCI, IF=3.576)

Vinay M. Shivanna, Kuan-Chou Chen, Bo-Xun Wu, and Jiun-In Guo,” A Comparison of Traditional and CNN Based Computer Vision Sensors for Detection and Recognition of Road Signs,” Chapter in the book: "Information Extraction and Object Tracking in Digital Video,"(http://www.intechopen.com/books/information-extraction-and-object-tracking-in-digital-video)ISBN:978-1-83969-461-5. https://www.intechopen.com/chapters/78576

Zohauddin Ahmad, Yan-Min Liao, Sheng-I Kuo, You-Chia Chang, Rui-Lin Chao, Naseem, Yi-Shan Lee, Yung-Jr Hung, Huang-Ming Chen, Jyehong Chen, Jiun-In Guo, and Jin-Wei Shi, “High-Power and High-Responsivity Avalanche Photodiodes for Self-Heterodyne FMCW Lidar System Applications,” IEEE Access, vol. 9, pp. 85661-85671, 2021. (SCI, IF=3.367)

Chia-Chi Tsai and Jiun-In Guo,” IVS-Caffe – Hardware-Oriented Neural Network Model Development,” IEEE Transactions on Neural Networks and Learning Systems (Accepted), March 27^th, 2021. (SCI, IF=8.793)

Chun-Yu Lai, Bo-Xun Wu, Vinay M. Shivanna, and Jiun-In Guo,” MTSAN: Multi-Task Semantic Attention Network for ADAS Applications,” IEEE Access, vol. 9, pp. 50700-50714, 2021. (SCI, IF=3.745)

Wen-Chia Tsai, Jhih-Sheng Lai, Kuan-Chou Chen, Vinay M. Shivanna and Jiun-In Guo, “A Lightweight Motional Objects Behavior Prediction System Harnessing Deep Learning Technology for Embedded ADAS Applications,” Electronics, Electrical and Autonomous Vehicles session, special issue Autonomous Vehicles Technology, vol. 10, issue 6, pp. 692, 2021. (SCIE, IF=2.412) (https://doi.org/10.3390/electronics10060692 (registering DOI))

Yu-Ting Li, Paul Kuo and Jiun In Guo, "Automatic Industry PCB Board DIP Process Defect Detection System based on Deep Ensemble Self-Adaption Method," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 11, issue 2, pp. 312-323, Feb. 2021. (SCI, IF=2.31) (ISSN: 2156-3950, Digital Object Identifier: 10.1109/TCPMT.2020.3047089)

Guan-Ting Lin, Vinay Malligere Shivanna, and Jiun-In Guo, “A Deep Learning Model with Task-Specific Bounding Box Regressors and Conditional Back-Propagation for Moving Object Detection in ADAS Applications,” Sensors, special issue on "Sensor and Communication Systems Enabling Autonomous Vehicles”, vol. 20, no. 18, pp. 1-21, Sept. 2nd, 2020. (SCIE, IF=3.275, rank: 77/266 in Engineering, Electrical and Electronic)

Jiun-In Guo, Chia-Chi Tsai, Jian-Lin Zeng, Shao-Wei Peng, and En-Chih Chang,” Hybrid Fixed Point/Binary Deep Neural Network Design Methodology for Low Power Object Detection,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), vol. 10, no. 3. pp. 388-400, September 2020. (SCI, 2018-2019 IF=4.643, article influence score (2018): 1.21, rank (2018): 65/266 in Engineering)

Chia-Chi Tsai, Cheng-Yen Lin, and Jiun-In Guo, "Dark channel prior based video dehazing algorithm with sky preservation and its embedded system realization for ADAS applications," Opt. Express, vol. 27, no. 9, pp. 11877-11901, April 2019. (SCI, IF=3.356, Eigenfactor Score: 0.19232, ranked 1^st out of 94 journals)

Jin-Wei Shi, Jiun-In Guo, Manabu Kagami, Paul Suni, and Olaf Ziemann, “Photonic technologies for autonomous cars: feature introduction,” Optics Express, vol. 27, no. 5, pp. 7627-7628, March, 2019. (SCI, IF=3.356, Eigenfactor Score: 0.19232, ranked 1^st out of 94 journals)

Po-Chun Shen, Kuan-Hung Chen, Jui-Sheng Lee, Guan-Yu Chen, Yi-Ting Lin, Bing-Yang Cheng, Guo-An Jian, Hsiu-Cheng Chang, Wei-Ming Lu, and Jiun-In Guo, “Intelligent Vision Processing Technology for Advanced Driver Assistance Systems,” A book chapter in Smart Sensors and Systems: Innovations for Medical, Environmental, and IoT Applications, ISBN 978-3-319-33200-0, pp.175-206, Springer, 2016.

Ching-Hwa Cheng, Chun-Hsiang Peng, Jiun-In Guo, Kai-Che Liu, Chi-Hsiang Wu,” A Two-Lens Minimally Invasive Surgical Panoramic Endoscope Design and Implementation,” International Journal of Electrical Engineering, 2015 (SCI, EI, invited paper).

Kuan-Hung Chen, Ting-Fung Ju, Wei-Ming Lu, and Jiun-In Guo,” Vision-Based Multiple Moving Objects Detection for Intelligent Automobiles,” International Journal of Electrical Engineering, vol. 21 no. 6, August, 2015 (SCI, EI, invited paper).

Ching-Hwa Cheng, Sheng-Wei Hsu, Cheng-An Chien, and Jiun-In Guo, “Using Voltage Difference to Design a Dual-Voltage Low-Power Multiple-mode Video Decoder,” International Journal of Electrical Engineering, vol. 19, no. 6, pp. 223-233, 2012. (SCI, EI)

Guo-An Jian, Cheng-An Chien, Peng-Sheng Chen, and Jiun-In Guo,” Real-Time 3D Depth Generation for Stereoscopic Video Applications with Thread-Level Superscalar-Pipeline Parallelization,” Journal of Signal Processing Systems, vol. 72, pp. 17-33, July 2013. (SCI, EI)

Guo-An Jian, Cheng-An Chien, Peng-Sheng Chen, Jiun-In Guo, ”A Verification-aware Design Methodology for Thread Pipelining Parallelization,” IEICE Transactions on Information and Systems, vol.E95-D, no.10, pp. Oct. 2012. (SCI, EI)

Cheng-An Chien, Guo-An Jian, Hsiu-Cheng Chang, Kuan-Hung Chen, and Jiun-In Guo,”High Efficiency Data Access System Architecture for Deblocking Filter Supporting Multiple Video Coding Standards,” IEEE Transactions on Consumer Electronics, vol. 58, no. 2, pp. 670-678, May 2012. (SCI, EI)

Jia-Wei Chen, Hsiu-Cheng Chang, Jinn-Shyan Wang, and Jiun-In Guo,“ A Dynamic Quality-Adjustable H.264 Intra Coder,” IEEE Transactions on Consumer Electronics, vol. 57, no. 3, pp. 1203-1211, August, 2011. (SCI, EI)

Jinn-Shyan Wang, Pei-Yao Chang, Tai-Shin Tang, Jia-Wei Chen, and Jiun-In Guo, " Design of Subthreshold SRAMs for Energy-Efficient Quality-Scalable Video Applications," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 1, no. 2, pp. 183-192, June 2011. (SCI, EI)

Ke Xu, Tsu-Ming Liu, Jiun-In Guo, and Chiu-Sing Choy, “Methods for Power/Throughput/Area Optimization of H.264/AVC Decoding,” Journal of Signal Processing Systems, Vol. 60, No. 1, pp. 131-145, July 2010. (SCI, EI)

Hsiu-Cheng Chang, Jia-Wei Chen, Bing-Tsung Wu, Ching-Lung Su, Jinn-Shyan Wang, and Jiun-In Guo, “ A Dynamic Quality-Adjustable H.264 Video Encoder for Power-Aware Video Applications,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 19, no. 12, pp. 1739-1754, Dec. 2009. (SCI, EI)

Wei-Chun Ku, Shu-Hsuan Chou, Jui-Chin Chu, Chi-Lin Liu, Tien-Fu Chen, Jiun-In Guo and Jinn-Shyan Wang, “VisoMT: A Collaborative Multithreading Multicore Processor for Multimedia Applications with a Fast Data Switching Mechanism,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 19, no. 11, pp. 1633-1645, November 2009. (SCI, EI)

Yao-Chang Yang, and Jiun-In Guo, “A High Throughput H.264/AVC High Profile CABAC Decoder for HDTV Applications,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 19, no. 9, pp. 1395-1399, September 2009. (SCI, EI)

Chih-Da Chien, Cheng-An Chien, Chien-Chang Lin, Ching-Hwa Cheng, and Jiun-In Guo,“ A 252Kgates/4.9Kbytes SRAM/71mW Multi-Standard Video Decoder for High Definition Video Applications,” ACM Transactions on Design Automation of Electronic Systems, vol. 14, no. 1, January 2009. (SCI, EI)

Chien-Chang Lin, Jia-Wei Chen, Hsiu-Cheng Chang, Yao-Chang Yang,Yi-Huan Ou Yang, Ming-Chih Tsai, Jiun-In Guo, and Jinn-Shyan Wang, “A 160K Gates/4.5KB SRAM H.264 Video Decoder for HDTV Applications,” IEEE Journal of Solid-State Circuits, vol. 42, no.1, pp. 170~182, January 2007. (SCI, EI)

Chih-Da Chien, Keng-Po Lu, Yu-Min Chen, Jiun-In Guo, Yuan-Sun Chu, and Ching-Lung Su,“An Efficient Variable Length Decoder IP Core Design for MPEG-1/2/4 Video Coding Applications,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 16, no.9, pp.1172-1178, September 2006. (SCI, EI)

Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, “An Efficient Direct 2-D Transform Coding IP Design for MPEG-4 AVC/H.264“, IEEE Transactions on Circuits and Systems for Video Technology, vol. 16, no. 4, pp.472-483, April 2006. (SCI, EI)

Hun-Chen Chen, Jiun-In Guo, Tian-Sheuan Chang, and Chein-Wei Jen, “A Memory Efficient Realization of Cyclic Convolution and its Application to Discrete Cosine Transform,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 15, no. 3, pp.445-453, March 2005. (SCI, EI)

Hun-Chen Chen, Tian-Sheuan Chang, Jiun-In Guo, and Chein-Wei Jen, “The Long Length DHT Design with A New Hardware Efficient Distributed Arithmetic Approach and Cyclic Preserving Partitioning,” IEICE Transactions on Electronics E88-C (5), pp. 1061-1069, May 2005. (SCI, EI)

Hun-Chen Chen, Jiun-In Guo, Chein-Wei Jen, and T. S. Chang, “Distributed arithmetic realisation of cyclic convolution and its DFT application,” IEE Proceedings: Circuits, Devices and Systems 152 (6), pp. 615-629, December 2005 (SCI, EI)

Chih-Da Chien, Chien-Chang Lin, Chung-Hang Yang, and Jiun-In Guo, “Design and Realization of a New Hardware Efficient IP Core for the 1-D Discrete Fourier Transform,” IEE Proceedings Circuits, Devices, and Systems, vol. 152, no. 3, pp. 247-258, June 2005. (SCI, EI)

Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh and Jia-Wei Chen, “A Power-Aware IP Core Design for the Variable-Length DCT/IDCT Targeting at MPEG4 Shape-Adaptive Transforms,” IEEE Transactions on Circuits and Systems for Video Technology, Special Issue on Integrated Multimedia Platforms, vol. 15, no. 5, pp. 704-715, May 2005. (SCI, EI)

J. I. Guo, Rei-Chin Ju, and Jia-Wei Chen, “An Efficient 2-D DCT/IDCT Core Design using Cyclic Convolution and Adder-based Realization,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 14, no. 4, pp. 416~428, April 2004. (SCI, EI)

Hun-Chen Chen, J. I. Guo, Lin-Chieh Huang, and Jui-Cheng Yen,”Design and Realization of a New Signal Security System for Multimedia Data Transmission,” EURASIP Journal on Applied Signal Processing, 2003:13, pp. 1291-1305. (SCI)

J. I. Guo and Jui-Cheng Yen, “An Efficient IDCT Processor Design for HDTV Applications,” Journal of VLSI Signal Processing, vol. 33, pp. 147-155, 2003. (SCI, EI)

J. I. Guo, Chih-Ta Chien, and Chien-Chang Lin, “A Low Power Parameterized Hardware Design for the One Dimensional Discrete FOURIER Transform of Variable Lengths,” Journal of Circuits, Systems, and Computers, vol. 11, no. 4, pp.405-426, 2002. (SCI, EI)

J. I. Guo, “A New Hardware Efficient Design Approach for the 1-D Discrete Fourier Transform,” Pattern Recognition and Image Analysis, vol.12, no.3, pp. 299-307, 2002.

J. I. Guo, Jui-Cheng Yen, and H. F. Pai, ”A New Voice Over Internet Protocol Technique with Hierarchical Data Security Protection,” IEE Proceedings- Visions, Images, and Signal Processing, vol. 149, no. 4, pp. 237-243, August 2002. (SCI, EI)

Jui-Cheng Yen and J. I. Guo, “The Design and Realization of a new Domino Signal Security System,” Journal of the Chinese Institute of the Electrical Engineering, vol.10, no.1, pp.69-76, 2003. (EI)

Jui-Cheng Yen and J. I. Guo, “The Design and Realization of a Chaotic Neural Signal Security System,” Pattern Recognition and Image Analysis, vol.12, no.1, pp.70-79, 2002.

J. I. Guo and C. C. Li, “A Generalized Architecture for the One Dimensional Discrete Cosine and Sine Transforms,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 11, no. 7, pp. 874-881, July 2001. (SCI, EI)

H. C. Chen, J. I. Guo, and Y. C. Tzeng, “Characterizations of Gate Delay in Cell Library using Dynamic Learning Neural Network,” Journal of National Lien-Ho Institute of Technology, vol. 17, pp.105-114, 2000.

T. S. Chang, J. I. Guo, and C. W. Jen,” Hardware Efficient DFT Designs with Cyclic Convolution and Subexpression Sharing,” IEEE Transactions on Circuits and Systems II, vol. 47, no. 9, pp. 886-892, Sep. 2000. (SCI, EI)

J. I. Guo, "Efficient Parallel Adder Based Design for One Dimensional Discrete Cosine Transform," IEE Proceedings Circuits, Devices, and Systems, vol.147, no. 5, pp.276-282, Oct. 2000. (SCI, EI)

J.  I. Guo, “An Efficient Design for One Dimensional Discrete Hartley Transform Using Parallel Additions,” IEEE Transactions on Signal Processing, vol. 48, no. 10, pp.2806~2813, Oct. 2000. (SCI, EI)

J. I. Guo, “A New Distributed Arithmetic Algorithm and its Hardware Architecture for the Discrete Hartley Transform,” Pattern Recognition and Image Analysis, vol.10, no.3, pp.368-378, 2000.

Jui-Cheng Yen and J. I. Guo, “A New Chaotic Mirror-Like Image Encryption Algorithm and its VLSI Architecture,” Pattern Recognition and Image Analysis, vol.10, no.2, pp.236-247, 2000.

Jui-Cheng Yen and J. I. Guo, “Efficient Hierarchical Chaotic Image Encryption Algorithm and its VLSI Realization,” IEE Proceedings, Vision, Image and Signal Processing, vol. 147, no. 2, pp. 167-175, April 2000. (SCI, EI)

J. I. Guo,” An Efficient Parallel Adder Based Design for One Dimensional Discrete Fourier Transform," Proceedings of the National Science Council, ROC, Part A, vol.24, no.3, pp.195-204, May 2000.

J. I. Guo,” A memory-based approach to design efficient VLSI arrays for the multi-dimensional discrete Hartley transform," Proceedings of the National Science Council, ROC, Part A, vol. 23, no.2, pp.289-302, 1999.

Jui-Cheng Yen, J. I. Guo, and Hun-Chen Chen,”A New k-Winners-Take-All Neural Network and Its Array Architecture,” IEEE Transactions on Neural Network, vol. 9, no 5, pp.901-912, September 1998. (SCI, EI)

J. I. Guo, C. M. Liu, and C. W. Jen,"A Novel CORDIC-Based Array Architecturefor the Multi-Dimensional Discrete Hartley Transform," IEEE Transactions on Circuits and Systems II, vol.42, no.5, pp.349-355, May 1995. (SCI, EI)

J. I. Guo, Chingson Chen, and C. W. Jen, "Unified architecture for discrete cosine transform, sine transform and their inverses," Electronics Letters, 12th October, vol.31, no.21, pp.1811-1812, 1995. (SCI, EI)

J. I. Guo, C. M. Liu, and C. W. Jen, "A New Array Architecture for Prime Length Discrete Cosine Transform," IEEE Transactions on Signal Processing, vol.41, no.1, pp.436-442, Jan. 1993. (SCI, EI)

J. I. Guo, C. M. Liu, and C. W. Jen, "The Efficient Memory-Based VLSI Array Designs for DFT and DCT," IEEE Transactions on Circuits and Systems, vol.39, no.10, pp.723-733, Oct. 1992. (SCI, EI)

Gerald Baulig, and Jiun-In Guo, “MIC-OPCC: Multi-Indexed Convolution model for Octree Point Cloud Compression,” Computer Graphics International 2025 (CGI2025), Kowloon, Hong-Kong, July 14-18, 2025. (4-page conference paper)

Gerald Baulig, and Jiun-In Guo, “MIC-OPCC: Multi Indexed Convolution model for Octree Point Cloud Compression,” IEEE 2025 Data Compression Conference (DCC2025), March 19-21, Snowbird, UT, USA, 2025. (one page summary)

Hsuan-Yu Lin, Yu-Cheng Yang, Xi-Liang Zhao, Jiun-In Guo, Yin-Tsung Hwang and Chih-Peng Fan, “Implementation of a Non-Contact Driver Monitoring System with Enhanced Object Detection and Pose Estimation,” Proc. 2024 IEEE 13th Global Conference on Consumer Electronics (GCCE), Oct. 29-Nov. 1, 2024, Kokura, Japan.

Yu-Shu Ni, Han-Chun, Chen, Chia-Chi Tsai, Chih-Cheng Chen, Po-Yu Chen, Hsien-Kai Kuo, Jun-Ying, Hunag, Po-Chi Hu, Jenq-Neng Hwang, and Jiun-In Guo, “SUMMARY OF THE 2024 LOW-POWER EFFICIENT AND ACCURATE FACIAL-LANDMARK DETECTION FOR EMBEDDED SYSTEMS,” Proc. 2024 IEEE International Conference on Multimedia and Expo (ICME2024), July 15-19, 2024, Niagra Falls, Canada.

Yu-ShuNi, Chia-Chi Tsai, Jyun-Syu Lin, Hsien-Po Meng, Po-Chi Hu, Jiun-Shiung Chen, Chih-Yuan Chuang, Jiun-In Guo, “Summary of the 2023 PAIR-LITEON Competition: Embedded AI Object Detection Model Design Contest on Fish-eye Around-view Cameras,” ACM Multimedia Asia Proceedings (MMAsia’23), Dec. 6-8, 2023, Tainan, Taiwan.

Yi-Chiao Fang, Xi-Liang Zhao, Hsuan-Yu Lin, Yu-Cheng Yang, Jiun-In Guo and Chih-Peng Fan, ”YOLO Deep-Learning Based Driver Behaviors Detection and Effective Gaze Estimation by Head Poses for Driver Monitor System,” Proc. 2023 IEEE 12th Global Conference on Consumer Electronics (GCCE), October 10-13, 2023, Nara, Japan.

Yu-Shu Ni, Chia-Chi Tsai, Chih-Cheng Chen, Hsien-Kai Kuo, Po-Yu Chen, Po-chi Hu, Ted Kuo, Jenq-Neng Hwang, Jiun-In Guo,” Summary of the 2023 Low-Power Deep Learning Object Detection and Semantic Segmentation Multi-Task Model Compression Competition for Traffic Scene in Asian Countries,” Proc. 2023 IEEE International Conference on Multimedia and Expo (ICME2023), July 10-14, 2023, Brisbane, Australia.

Cheng-Fu Liou, Tsung Han Lee and Jiun-In Guo, "Asynchronous Multi-Task Learning Based on One Stage YOLOR Algorithm" Proc. IEEE 32nd International Symposium on Industrial Electronics (ISIE2023), June 19^th-21^th, 2023, Aalto University, Helsinki-Espoo, Finland.

Po-Yuan Chen, Hung-Che Lin, Jiun-In Guo,” "Multi-Scale Dynamic Fixed-Point Quantization and Training for Deep Neural Networks", Proc. 2023 IEEE International Symposium on Circuits & Systems (ISCAS2023), Monterey, May 21 - 25, 2023, California, USA.

An-Tai Hsiao, Chun-Hsien Liu, Po-Hsuan Chen, Yao-Lun Liu, Wei-Chi Wang, Tzu-Hsien Sang, Chia-Ming Tsai, Gray Lin, Jiun-In Guo, and Sheng-Di Lin,” Real-time LiDAR module with 64x128-pixel CMOS SPAD array and 940-nm PCSEL,” Proc. 2022 IEEE Sensors Applications Symposium (SAS), August 1-3, 2022, Sundsvall, Sweden.

Yu-Shu Ni, Chia-Chi Tsai, Chih-Cheng Chen, Po-Yu Chen, Hsien-Kai Kuo, Man-Yu Lee, Chin-Chuan, Kuo, Zhe-Ln Hu, Po-Chi Hu, Ted T. Kuo, Jenq-Neng Hwang, and Jiun-In Guo,” Summary of the 2022 Low-Power Deep Learning Semantic Segmentation Model Compression Competition for Traffic Scene in Asian Countries,” Proc. 2022 IEEE International Conference on Multimedia and Expo (ICME2022), July 18-22, 2022, Taipei, Taiwan.

Bo-Xun Wu, Jia-Jheng Lin, Hsien-Kai Kuo, Po-Yu Chen, and Jiun-In Guo, “Radar and Camera Fusion for Vacant Parking Space Detection,” Proc. IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS2022), Songdo Convensia, Incheon, Korea, June 13-15, 2022.

Cheng-Fu Liou, Li-Ting Huang, Paul Kuo, Chien-Kuo Wang, Jiun-In Guo, “AI-Assisted STANFORD Classification of Aortic Dissection in CT Imaging Using Volumetric 3D CNN with External Guided Attention" Proc. 2021 IEEE Biomedical Circuits and Systems Conference (BioCAS2021), Berlin, Germany, Oct. 6-9, 2021.

Yu-Shu Ni, Chia-Chi Tsai, Bo-Xun Wu, Jia-Jheng Lin, Jen Shuo Chang, Po-Chi Hu, Ted T. Kuo, Jenq-Neng Hwang, Po-Yu Chen, Hsienkai Kuo, and Jiun-In Guo, “Summary on The 2021 Embedded Deep Learning Object Detection Model Compression Competition for Traffic in Asian Countries,” Proc. 2021 ACM International Conference on Multimedia Retrieval (ICMR2021), Taipei, Taiwan, August 21-24, 2021.

Cheng-Fu Liou, Paul Kuo, and Jiun In Guo, “Residual Knowledge Retention For Edge Devices,” Proc. 2021 IEEE 30th International Symposium on Industrial Electronics (ISIE2021), June 20-23, 2021, Kyoto, Japan.

Tsung Han Lee*, Li-Ting Huang, Po Tsun, Paul Kuo, Chien-Kuo Wang, Jiun In Guo, “FOCAL-BALANCED ATTENTION U-NET WITH DYNAMIC THRESHOLDING BY SPATIAL REGRESSION FOR SEGMENTATION OF AORTIC DISSECTION IN CT IMAGERY,” Proc. 2021 IEEE International Symposium on Biomedical Imaging (ISBI) (ISBI 2021), Nice, France, April 13-16, 2021.

Bo-Hong Lin, Hou-Zhen Cheng, Yu-Ting Li, and Jiun-In Guo,” 360 Degree Fish Eye Optical Construction for Equirectangular Projection of Panoramic Images,” Proc. The International Conference on Pervasive Artificial Intelligence (ICPAI2020), Taipei, Taiwan, Dec. 3-5, 2020.

Chun-Yu Lai, Bo-Xun Wu, Tsung-Han Lee, Vinay, and Jiun-In Guo,” A Light Weight Multi-Head SSD Model for ADAS Applications,” Proc. The International Conference on Pervasive Artificial Intelligence (ICPAI2020), Taipei, Taiwan, Dec. 3-5, 2020.

Jian Xian Lu, Jia Cheng Lin, Vinay Malligere Shivanna, Po-Yu Chen, Jiun-In Guo,” Fusion Technology of Radar and RGB Camera Sensors for Object Detection and Tracking and its Embedded System Implementation,” Proc. APSIPA ASC 2020, Auckland, New Zealand, Dec. 7-10, 2020.

Tsung-Han Lee, Hung-Wei Lin and Jiun-In Guo, “Deep Learning Object Detection, Tracking, and Recognition System for UAV Applications,” Proc. The 31th VLSI Design/CAD Symposium, August 4-7, 2020, Taichung, Taiwan.

Wen-Chia Tsai, Kuan-Chou Chen, Jhih-Sheng Lai and Jiun-In Guo, “Front Moving Object Behavior Prediction System Exploiting Deep Learning Technology for ADAS Applications,” Proc. 63rd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS2020), August 9th-12th, 2020, Springfield, MA, USA.

Yu Ting Li, Paul Kuo, Jiun-In Guo,” Automatic Industry PCB Board DIP Process Defect Detection with Deep Ensemble Method,” Proc. 2020 IEEE 29th International Symposium on Industrial Electronics (ISIE2020), June 17-19, 2020, Delft, Netherlands.

Chia-Chi Tsai, Yong-Hsiang Yang, Hung-Wei Lin, Bo-Xun Wu, En Chih Chang , Hung Yu Liu, Jhih-Sheng Lai, Po Yuan Chen, Jia-Jheng Lin, Jen Shuo Chang, Li-Jen Wang, Ted T. Kuo, Jenq-Neng Hwang, and Jiun-In Guo, “The 2020 Embedded Deep Learning Object Detection Model Compression Competition for Traffic in Asian Countries,” Proc. 2020 IEEE International Conference on Multimedia and Expo (ICME2020), July 6-10, 2020, London, United Kingdom.

Ching-Hwa Cheng and Jiun-In Guo, “Low-Power 3D-PCB Stacking System Design and Validation by Automatic Voltage-Current Scalable Technique,” Proc. 2020 International Symposium on VLSI Design, Automation & Test (VLSI-DAT), April 20-23, Hsinchu, Taiwan, 2020.

Zi-Yi Zhao, An-Tai, Xiao, and Jiun-In Guo, ”Video Dehazing Hardware Accelerator Design based on Dark Channel Prior with Sky Preservation,” Proc. 2020 International Symposium on VLSI Design, Automation & Test (VLSI-DAT), April 20-23, Hsinchu, Taiwan, 2020.

Jiun-In Guo, Chia-Chi Tsai, Yong-Hsiang Yang, Hung-Wei Lin, Bo-Xun Wu, Ted T. Kuo, and Li-Jen Wang,” Summary-Embedded Deep Learning Object Detection Model Competition in IEEE MMSP 2019,” Proc. IEEE 21st International Workshop on Multimedia Signal Processing (MMSP 2019), Kuala Lumpur, Malaysia, Sept. 27-29, 2019.

Yi-Hsuan Hsu and Jiun-In Guo, ”A Real-time and Online Multiple-Type Object Tracking Method with Deep Features,” Proc. APSIPA ASC 2019, Lanzhou, China, Nov. 18-21, 2019.

Yu-Ting, Li and Jiun-In Guo, ”A Robust Faster RCNN Network for PCB Defect Inspection,” The 30th VLSI Design/CAD Symposium, August 2019, Taiwan.

Yi-Hsuan Hsu and Jiun-In Guo, ”A Low Power Deep Learning Method for Object Identification,” The 30th VLSI Design/CAD Symposium, August 2019, Taiwan.

Ching-Hwa Cheng, Xiang-Ren Yang, and Jiun-In Guo, “Using 3D-PCB Stacking System to Design a Low-Power Two-Lenses Wireless Panoramic Micro-Endoscopy”, The 30th VLSI Design/CAD Symposium, August 2019, Taiwan.

Ching-Hwa Cheng, An-Tia Xiao, and Jiun-In Guo, “Quadruple-Voltage Power-Performance Optimized H.264 Video Encoder Chip Design and Validation”, The 30th VLSI Design/CAD Symposium, August 2019, Taiwan.

Ching-Kan Tseng, Chia-Chi Tsai, and Jiun-In Guo, “Pvalite CLN: Lightweight Object Detection with Classfication and Localization Network,” Proc. IEEE 32^nd International System-on-Chip Conference (SOCC 2019), September 3-5, Marina Bay Sands Hotel, Singapore, 2019.

Kuan-Chou Chen, Guan-Ting Lin, Che-Tsung Lin, Jiun-In Guo, “RECOGNIZING CHINESE TEXTS WITH 3D CONVOLUTIONAL NEURAL NETWORK,” Proc. IEEE International Conference on Image Processing (ICIP 2019), September 22-25, Taipei, Taiwan, 2019.

Ching-Kai Tseng, Chien-Chih Liao, Po-Chun Shen, Jiun-In Guo, “USING C3D TO DETECT REAR OVERTAKING BEHAVIOR,” Proc. IEEE International Conference on Image Processing (ICIP 2019), September 22-25, Taipei, Taiwan, 2019.

Guan-Ting Lin, Patrisia Sherryl Santoso, Che-Tsung Lin, Chia-Chi Tsai, Jiun-In Guo,” One Stage Detection Network with an Auxiliary Classifier for Real-Time Road Marks Detection,” Proc. APSIPA ASC 2018, Honolulu Hawaii, USA, 12-15 Nov. 2018.

Chia Chi Tsai, Ching-Kan Tseng, Ho-Chia Tang, Jiun-In Guo, “Vehicle Detection and Classification based on Deep Neural Network for Intelligent Transportation Applications,” Proc. APSIPA ASC 2018, Honolulu Hawaii, USA, 12-15 Nov. 2018.

Yi-Hsuan Hsu, Ssu-Yuan Chang and Jiun-In Guo,” A Multiple Vehicle Tracking and Counting Method and its Realization on an Embedded System with a Surveillance Camera,” Proc. IEEE International Conference on Consumer Electronics-Taiwan (IEEE ICCE-TW 2018), May 19-21, Taichung, Taiwan, 2018.

Yu Ting Li, and Jiun In Guo,” A VGG-16 based Faster RCNN Model for PCB Error Inspection in Industrial AOI Applications,” Proc. IEEE International Conference on Consumer Electronics-Taiwan (IEEE ICCE-TW 2018), May 19-21, Taichung, Taiwan, 2018.

Guan-Ting Lin and Jiun-In Guo,” Efficient and Lightweight Convolutional Neural Network for Lane Mark and Road Segmentation,” Proc. IEEE International Conference on Consumer Electronics-Taiwan (IEEE ICCE-TW 2018), May 19-21, Taichung, Taiwan, 2018.

Bo-Xun Wu, Pin-Yu Wang, Yi-Ta Yang, and Jiun-In Guo,” Traffic Sign Recognition with Light Convolutional Networks,” Proc. IEEE International Conference on Consumer Electronics-Taiwan (IEEE ICCE-TW 2018), May 19-21, Taichung, Taiwan, 2018.

Shun-Min Chang, Chia-Chi Tsai and Jiun-In Guo,” A Blind Spot Detection Warning System based on Gabor Filtering and Optical Flow for E-mirror Applications, Proc. 2018 IEEE Int'l Symposium on Circuits & Systems (ISCAS 2018), Florence, Italy, May 27-30, 2018.

Tai-En Wu, Chia-Chi Tsai, and Jiun-In Guo,” LiDAR/Camera Sensor Fusion Technology for Pedestrian Detection,” Proc. APSIPA ASC 2017, Kuala Lumpur, Malaysia, 12-15 Dec. 2017.

Guan-Ting Lin, Patrisia Sherryl Santoso, Che-Tsung Lin, Chia-Chi Tsai and Jiun-In Guo,” Stop Line Detection and Distance Measurement for Road Intersection based on Deep Learning Neural Network,” Proc. APSIPA ASC 2017, Kuala Lumpur, Malaysia, 12-15 Dec. 2017.

Yuan-Fu Li, Chia-Chi Tsai, Yi-Ting Lai, and Jiun-In Guo,” A Multiple-Lane Vehicle Tracking Method for Forward Collision Warning System Applications,” Proc. APSIPA ASC 2017, Kuala Lumpur, Malaysia, 12-15 Dec. 2017.

Tai-En Wu, Chia-Chi Tsai, and Jiun-In Guo,” LiDAR/Camera Sensor Fusion Technology for Pedestrian Detection,” Proc. 2017 VLSI Design/CAD Symposium, Kenting, Taiwan, August 1-4, 2017.

Ssu-Yuan Chang, and Jiun-In Guo, “Multiple People Tracking and Couting Methods based on Single Camera,” Proc. 2017 VLSI Design/CAD Symposium, Kenting, Taiwan, August 1-4, 2017.

Yi-Ting Lai, Chia-Chi Tsai, and Jiun-In Guo, “Lane Departure Warning System Combining with Curve Lane Detection for Lane Keeping Applications,” Proc. 2017 VLSI Design/CAD Symposium, Kenting, Taiwan, August 1-4, 2017.

Shun-Min Chang and Jiun-In Guo, “A Blind Spot Detection Warning System based on Gabor Filtering and Optical Flow,” Proc. 2017 VLSI Design/CAD Symposium, Kenting, Taiwan, August 1-4, 2017.

Fong-An Chang, Chia-Chi Tsai, Ching-Kan Tseng and Jiun-In Guo,” Embedded Multiple Object Detection Based on Deep Learning Technique for Advanced Driver Assistance System,” Proc. IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS 2017), August 6-9, Boston, MA, USA, 2017.

Ting Chou, Ssu-Yuan Chang, Vinay M.S. and Jiun-In Guo, “Triangular Road Signs Detection and Recognition  Algorithm and its Embedded System Implementation,” Proc. The 21th International Conference on Image Processing, Computer Vision & Pattern Recognition (IPCV'17), July 17-20, 2017, Las Vegas, USA.

Ricky Lee and Jiun-In Guo,” An Adaptive Cross-window Stereo Camera Distance Estimation Technology and its System Implementation for Multiple Applications,” Proc. 2017 International Symposium on VLSI Design, Automation & Test (VLSI-DAT), April 24-27, Hsinchu, Taiwan, 2017.

Chia-Chi Tsai, Yi-Ting Lai, Yuan-Fu Li, and Jiun-In Guo, “A Vision Radar System for Car Safety Driving Applications,” Proc. 2017 International Symposium on VLSI Design, Automation & Test (VLSI-DAT), April 24-27, Hsinchu, Taiwan, 2017.

Jiun-In Guo, Kai-Che Liu, Chia-Chi Tsai, Jan Yang Lin, Yong-Cyuan Yang, Ching-Hwa Cheng, Jungle Chi-Hsiang Wu, and Shih-Wei Huang, “Real-time Image Processing Method for Laparoscope Defogging,” Proc. SAGES 2017 Annual Meeting, March 22-25, Houston TX, USA.

Chuan-Chung, Chang, Hsin-Hsiang, Lo, Han-Hsuan, Lin, Zhi-Rong, Fan, Shao-Hsuan, Cheng, Chih-Hung, Lu, Fu-Ming, Chuang, Jiun-In, Guo, “Localized High Dynamic Range Plenoptic Image Compression,” Proc. of 2017 IS&T International Symposium on Electronic Imaging 2017 (EI 2017), Jan. 29^th-Feb. 2^nd, Burlingame, California, USA, 2017.

Chun-Yu Chung, Yi-Ting Lai, and Jiun-In Guo,” Design and Implementation of a Dangerous Driving Behavior Analysis System”, Proc. 2016 International Symposium on VLSI Design, Automation & Test (VLSI-DAT), April 25-27, Hsinchu, Taiwan, 2016.

Chia-Jui Yang, Ting Chou, Fong-An Chang, and Jiun-In Guo,” A Smart Surveillance System with Multiple People Detection, Tracking, and Behavior Analysis”, Proc. 2016 International Symposium on VLSI Design, Automation & Test (VLSI-DAT), April 25-27, Hsinchu, Taiwan, 2016.

Yi-Ting Lin, Ting Chou, Vinay M.S, and Jiun-In Guo,” Algorithm derivation and its embedded system realization of speed limit detection for multiple countries,” Proc. 2016 IEEE Int'l Symposium on Circuits & Systems, Montreal, Canada, May 22-26, 2016.

Sheng-Wei Hsu, Zhi-Rong Fan, Jan Yang Lin and Jiun-In Guo, “Endoscopy Image De-fogging based on Dynamic Local Contrast Enhancement,” Proc. 2016 Symposium on Engineering Medicine and Biology Applications, Jan. 22-24, Tao-Yuan, Taiwan, 2016.

Ching-kwok Lau, Vinay M. S., and Jiun-In Guo, “Stomach Ulcer Detection Using Multiple Feature Extraction,” Proc. 2016 Symposium on Engineering Medicine and Biology Applications, Jan. 22-24, Tao-Yuan, Taiwan, 2016.

An-Tai Xiao, Yung-Siang Miao, Ching-Hwa Cheng, and Jiun-In Guo, “A Variable-Voltage Low-Power Technique for Digital Circuit System,” Proc. the 21st Asia and South Pacific Design Automation Conference-University Design Contest (ASP-DAC UDC 2016), Jan. 25-28, Macao, China, 2016.

Bing-Yang Cheng, Jui-Sheng Lee, and Jiun-In Guo, “An AdaBoost Object Detection Design for Heterogeneous Computing with OpenCL,” Proc. IEEE International Conference on Consumer Electronics-Taiwan (IEEE ICCE-TW 2015), June 6-8, 2015, Taipei, Taiwan, 2015.

Ching-Hwa Cheng, Sheng-Ping Hung, Jiun-In Guo, Kai-Che Liu, Chi-Hsiang Wu, “A Wireless Panoramic Endoscope System Design and Implementation for Minimally Invasive Surgery, “, Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Live Demonstration, May 24 – 27, Portugal, Lisbon, 2015.

Po-Yu Chien, Yuan-Hsiang Miao, and Jiun-In Guo,” A 3D Hand Tracking Design for Gesture Control in Complex Environments,” Proc. 2015 International Symposium on VLSI Design, Automation & Test (VLSI-DAT), April 27-29, Hsinchu, Taiwan, 2015.

An-Tia Xiao, Yuan-Hsiang Miao, Shiang-Ren Yang, Ching-Hwa Cheng, Jiun-In Guo, “A Power-Aware Quad-Voltage H.264 Encoder Chip for Wireless Panoramic Endoscope Applications,” Proc. 2015 International Symposium on VLSI Design, Automation & Test (VLSI-DAT), April 27-29, Hsinchu, Taiwan, 2015.

Po-Hsiang Huang, Yuan-Hsiang Maio and Jiun-In Guo,” High Dynamic Range Imaging Technology for Micro Camera Array,” Proc. APISPA ASC 2014, Siem Reap, city of Angkor Wat, Cambodia, Dec. 9-12, 2014.

Che-Cheng Li, Sheng-Wei Hsu, Po-Chun Shen and Jiun-In Guo,” A Single-Camera High Dynamic Range Technique by Using Contrast Enhancement and Exposure Control,” Proc. APISPA ASC 2014, Siem Reap, city of Angkor Wat, Cambodia, Dec. 9-12, 2014.

Sheng-Wei Hsu, Guan-Yu Chen, Po-Chun Shen and Jiun-In Guo,” Inclement Weather Condition Processing Method for Advanced Driver Assistance System,” Proc. 2014 VLSI Design/CAD Symposium, Taichung, Taiwan, August 5-8, 2014.

Shiang-Ren Yang, An-Tia Xiao, Yuan-Hsiang Miao, Ching-Hwa Cheng, Jiun-In Guo,” A Power-Aware Quad-Voltage H.264 Encoder Chip for Wireless Panoramic Endoscope Applications,” Proc. 2014 VLSI Design/CAD Symposium, Taichung, Taiwan, August 5-8, 2014.

Chun-Hsiang Peng, Ching-Hwa Cheng, Jiun-In Guo,” A Panoramic Endoscope System Design and Implementation for Minimally Invasive Surgery,” Proc. 2014 VLSI Design/CAD Symposium, Taichung, Taiwan, August 5-8, 2014.

Guan-Yu Chen, Po-Chun Shen, Chao-Yi Cho, Vinay M.S, and Jiun-In Guo,” A Forward Collision Avoidance System Adopting Multi-feature Vehicle Detection,” Proc. IEEE International Conference on Consumer Electronics-Taiwan (IEEE ICCE-TW 2014), May 26-28, 2014, Taipei, Taiwan, 2014.

Jui-Sheng Lee, Hsiu-Cheng Chang, and Jiun-In Guo,” An Adaboost-based Two-level Moving Object Detection Architecture with Dynamic ROI Allocation,” Proc. IEEE International Conference on Consumer Electronics-Taiwan (IEEE ICCE-TW 2014), May 26-28, 2014, Taipei, Taiwan, 2014.

Chingwei Yeh, Chun-Hao Hsu, Po-Chun Hung, Tay-Jyi Lin, Chen-Yao Tsai, and Jiun-In Guo,” Maintaining Color Fidelity for Dual-Shot HDR Imaging,” Proc. IEEE International Conference on Consumer Electronics-Taiwan (IEEE ICCE-TW 2014), May 26-28, 2014, Taipei, Taiwan, 2014.

Ting-Fung Ju, Wei-Min Lu, Kuan-Hung Chen, and Jiun-In Guo,” Vision-Based Moving Objects Detection for Intelligent Automobiles and a Robustness Enhancing Method,” Proc. IEEE International Conference on Consumer Electronics-Taiwan (IEEE ICCE-TW 2014), May 26-28, 2014, Taipei, Taiwan, 2014.

Sheng-Wei Hsu, Guan-Yu Chen, Po-Chun Shen, and Jiun-In Guo, “Dynamic Local Contrast Enhancement for Advanced Driver Assistance System in Harsh Environments,” Proc. IEEE International Conference on Consumer Electronics-Taiwan (IEEE ICCE-TW 2014), May 26-28, 2014, Taipei, Taiwan, 2014.

Kai-Chen Huang, Po-Yu Chien, Cheng-An Chien, Hsiu-Cheng Chang and Jiun-In Guo,” A 360-degree Panoramic Video System Design,” Proc. 2014 International Symposium on VLSI Design, Automation & Test (VLSI-DAT), April 28-30, Hsinchu, Taiwan, 2014.

Yuan-Hsiang Miao, Guo-An Jian, Li-Ching Wang, Jui-Sheng Lee, and Jiun-In Guo,” A Low Complexity Multi-view Video Encoder Exploiting B-frame Characteristics,” Proc. APSIPA-ASC 2013, Oct. 29-Nov. 1, Kaohsiung, Taiwan, 2013.

Ching-Hwa Cheng, Sheng-Wei Hsu, Jiun-In Guo, “A Low-Cost In-Die Scalable Voltage-Frequency Adjustor for Low-Power System Implementation,” Proc. 2013 International Symposium on Circuits and Systems, May 19-23, Beijing, China, 2013.

Guo-An Jian, Jui-Sheng Lee, Kheng-Joo Tan, Peng-Sheng Chen, and Jiun-In Guo, “A Real-time Parallel Scalable Video Encoder for Multimedia Streaming Systems,” Proc. 2013 International Symposium on VLSI Design, Automation & Test (VLSI-DAT), April 22-24, Hsinchu, Taiwan, 2013.

Jui-Sheng Lee, Yuan-Hsiang Miao, Cheng-An Chien, Hsiu-Cheng Chang and Jiun-In Guo, “A View Scalable Multi-View Video Decoder System,” Proc. 2013 International Symposium on VLSI Design, Automation & Test (VLSI-DAT), April 22-24, Hsinchu, Taiwan, 2013.

Ching-Hwa Cheng, Sheng-Wei Hsu, Cheng-An Chien, and Jiun-In Guo,” A Voltage-Current Adjusted Low-Power Video Decoder Design and Implementation for Wireless Panoramic Endoscope,” Proc. SEMBA, Feb. 2013.

Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, Ting-Yu Shyu, Chien-Yung Chou, Shien-Chun Luo, Jiun-In Guo, Tien-Fu Chen, Yuan-Hua Chu, Liang-Chia Cheng, Hong-Men Su, Chewnpu Jou, Meikei Ieong, Cheng-Wen Wu, Gene C.H. Chuang, Jinn-Shyan Wang, “A 0.48V 0.57nJ/Pixel Video Recording SoC in 65nm CMOS,” Proc. 2013 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, Session 9.3, Feb. 2013.

Jui-Sheng Lee, Sheng-Han Wang, Chih-Tai Chou, Cheng-An Chien, Hsiu-Cheng Chang and Jiun-In Guo, “An Inter-frame/Inter-view Cache Architecture Design for Multi-view Video Decoders,” Proc. APSIPA-ASC 2012, Dec. 3-6, Hollywood, California, USA, 2012.

Jui-Sheng Lee, Cheng-An Chien, and Jiun-In Guo, “3d depth map generation for Embedded stereo applications,” Proc. Visual Communications and Image Processing (VCIP), Nov. 27-30, SanDiego, USA, 2012.

Cheng-An Chien, Cheng-Yen Chang, Hsiu-Cheng Chang, Jia-Wei Chen, and Jiun-In Guo,” A Two Level Mode Decision Algorithm for H.264 High Profile Encoder,” Proc. 2012 IEEE International Symposium on Circuits and Systems (ISCAS), May 20-23, Seoul, Korea, 2012.

Ching-Hwa Cheng, and Jiun-In Guo,” A High-Speed Dual-Phase Processing Pipelined Domino Circuit Design with a Built-in Performance Adjusting Mechanism,” Proc. 2012 International Symposium on VLSI Design, Automation & Test (VLSI-DAT), April 23-25, Hsinchu, Taiwan, 2012.

Sheng-Wei Fan, Jia-Wai Chen, and Jiun-In Guo, “Low Bandwidth HD1080@60fps JPEG-XR Transform Design,” Proc. 2012 International Symposium on VLSI Design, Automation & Test (VLSI-DAT), April 23-25, Hsinchu, Taiwan, 2012.

Jia-Wei Chen, Pei-Yao Chang, Keng-Jui Chang, Tzu-Yuan Kuo, Wei-Han Hsu, Cheng-An Chien, Hsiu-Cheng Chang, Jinn-Shyan Wang, and Jiun-In Guo,” A 0.5V 25Mpixels/s SVGA 30fps H.264 Video Decoder Chip,” Proc. 2011 International Symposium of Integrated Circuits (ISIC-2011), December 12-14, Singapore, 2011.

Alan P. Su, Jiff Kuo, Kuen-Jong Lee, Ing-Jer Huang, Guo-An Jian, Cheng-An Chien, Jiun-In Guo, and Chien-Hung Chen, "GPrime II – A Multi-core Software/Hardware Co-debug Platform," Proc. DAC Workshop on Diagnostic Services in Network-on-Chips (DSNoC), June 5, San Diego, USA, 2011.

Alan P. Su, Jiff Kuo, Kuen-Jong Lee, Ing-Jer Huang, Guo-An Jian, Cheng-An Chien, Jiun-In Guo, and Chien-Hung Chen, "A Multi-core Software/Hardware Co-debug Platform with ARM CoreSight^TM, On-chip Test Architecture and AXI/AHB Bus Monitor," Proc. 2011 International Symposium on VLSI Design, Automation & Test (VLSI-DAT), April 25-27, Hsinchu, Taiwan, 2011.

Cheng-An Chien, Yao-Chang Yang, Feng-Ming Yang, Jia-Wai Chen, Hsiu-Cheng Chang, and Jiun-In Guo, “An AVS/H.264 Dual Mode Video Decoder Targeted at High Definition Video Applications,” Proc. 2011 International Symposium on VLSI Design, Automation & Test (VLSI-DAT), April 25-27, Hsinchu, Taiwan, 2011.

Yu-Tzn Tsai, Hsiang-Hui Huang, Ching-Hwa Cheng, and Jiun-In Guo, “A Low-Power VDD-Management Technique for High-Speed Domino Circuits,” Proc. 2011 International Symposium on VLSI Design, Automation & Test (VLSI-DAT), April 25-27, Hsinchu, Taiwan, 2011.

Cheng-An Chien, Cheng-Yen Chang, Jui-Sheng Lee, Jia-Hou Chang, and Jiun-In Guo,” Low Complexity 3D Depth Map Generation for Stereo Applications,” Proc. International Conference on Consumer Electronics (ICCE’2011), Jan. 9-12, Las Vegas, USA, 2011.

Dou-Cheng Chang, Cheng-An Chien, and Jiun-In Guo,” A Low-Complexity Image Stitching Algorithm Suitable for Embedded Systems,” Proc. International Conference on Consumer Electronics (ICCE’2011), Jan. 9-12, Las Vegas, USA, 2011.

Yu-Tzu Tsai, Cheng-Chih Tsai, Cheng-An Chien, Ching-Hwa Cheng, and Jiun-In Guo, “Dual-Phase Pipeline Circuit Design Automation with a Built-in Performance Adjusting Mechanism,” Proc. IEEE 16th Asia and South Pacific Design Automation Conference (ASP-DAC’2011), Jan. 25~28, Yokohama, Japan, 2011.

Yu-Tzu Tsai, Cheng-Chih Tsai, Cheng-An Chien, Ching-Hwa Cheng, and Jiun-In Guo, “A Low-Power Management Technique for High-Performance Domino Circuits,” Proc. IEEE 16th Asia and South Pacific Design Automation Conference (ASP-DAC’2011), Jan. 25~28, Yokohama, Japan, 2011.

Cheng-An Chien, Yao-Chang Yang, Hsiu-Cheng Chang, Jia-Wei Chen, Cheng-Yen Chang, Jiun-In Guo, Jinn-Shan Wang, and Ching-Hwa Cheng, “A H.264/MPEG-2 Dual Mode Video Decoder Chip Supporting Temporal/Spatial Scalable Video,” Proc. IEEE 16th Asia and South Pacific Design Automation Conference (ASP-DAC’2011), Jan. 25~28, Yokohama, Japan, 2011.

Ping-Tsung Wu, and Jiun-In Guo, “Low Compute Complexity BU-Based Rate Control Algorithm for H.264/AVC Encoder,” Proc. 2010 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS’2010), Kuala Lumpur, Malaysia, Dec. 6-9, 2010.

Ping-Tsung Wu, and Jiun-In Guo, “Low Compute Complexity BU-Based Rate Control Algorithm for H.264/AVC Encoder,” Proc. 2010 VLSI Design/CAD Symposium, Kaohsiung, Taiwan, August 3-6, 2010.

Cheng-An Chien, Yi-Chuang Liang, Jia-Wei Chen and, Jiun-In Guo,” Low Complexity H.264/AVS Predictive Pixel Compensator for HDTV Applications,” Proc. 2010 VLSI Design/CAD Symposium, Kaohsiung, Taiwan, August 3-6, 2010.

Cheng-An Chien, Cheng-Yen Chang, Jui-Sheng Lee, Jia-Hou Chang, and Jiun-In Guo, “Low Complexity 3D Depth Map Generation for Stereo Applications,” Proc. 2010 VLSI Design/CAD Symposium, Kaohsiung, Taiwan, August 3-6, 2010.

Yap-Chung Phong, Ching-Hwa Cheng, and Jiun-In Guo, “An Efficient Peak Current Alleviation Methodology Using Threshold Voltage Adjusting with Gate Sizing Techniques,” Proc. International Conference on Green Circuits and Systems (ICGCS 2010), June 21-23, Shanghai, P. R. China, 2010.

Cheng-An Chien, Ching-Hwa Cheng, and Jiun-In Guo, “A Clock-Controlled Self-Stabilized Voltage Technique with High Dynamic Power Reduction for Portable Multimedia Applications,” Proc. International Conference on Green Circuits and Systems (ICGCS 2010), June 21-23, Shanghai, P. R. China, 2010.

Chih-Chuan Yang, Kheng-Joo Tan, Yao-Chang Yang, and Jiun-In Guo, “Low Complexity Fractional Motion Estimation with Adaptive Mode Selection for H.264/AVC,” Proc. 2010 IEEE International Conference on Multimedia & Expo (ICME 2010), Singapore, July 19-23, 2010.

Kheng-Joo Tan, Hsin-Yi Li, Bing-Tsung Wu, Dou-Cheng Chang, Jia-Wei Gong, Yi-Mao Hsiao, Yung-Chung Chen, Shi-Wu Lo, Yuan-Sun Chu, and Jiun-In Guo, “A Remote Thin Client System for Real Time Multimedia Streaming Over VNC,” Proc. 2010 IEEE International Conference on Multimedia & Expo (ICME 2010), Singapore, July 19-23, 2010.

Chang-Hung Tsai, Kheng-Joo Tan, Ching-Lung Su, and Jiun-In Guo, “A Group of Macroblock Based Motion Estimation Algorithm Supporting Adaptive Search Range for H.264 Video Coding,” Proc. 2010 IEEE International Symposium on Circuits and Systems (ISCAS 2010), May 30- June 2, Paris, France, 2010.

Ping-Tsung Wu, Tzu-Chun Chang, Ching-Lung Su, and Jiun-In Guo, “A BU-based Rate Control Design for H.264 and AVS Video Coding with ROI Support,” Proc. 2010 International Symposium on VLSI Design, Automation & Test (VLSI-DAT), April 26-29, Hsinchu, Taiwan, 2010.

Elone Lee, Feng-Tso Chien, Ching-Hwa Cheng, and Jiun-In Guo, “Dynamic Voltage Domain Assignment Technique for Low Power Performance Manageable Cell Based Design,” Proc. IEEE The 15th Asia and South Pacific Design Automation Conference" (ASP-DAC 2010), Taipei, Taiwan, January 18-21, 2010.

Tao-Cheng Chang, Hung-Wei Shen and Jiun-In Guo, “A Low Complexity Error Concealment Method for H.264 Video Coding Facilitating Hardware Realization,” Proc. The 10^th International Symposium on Pervasive Systems, Algorithms and Networks (I-SPAN 2009), Kao-Hsiung, Taiwan, December 14-16, 2009.

Ching-Lung Su, Tse-Min Chen, Chih-Yang Huang, Shau-Yin Tseng, and Jiun-In Guo, “An Motion Estimation Algorithm with Low Memory and Bandwidth Requirements for H.264/AVC Scalable Extension,” Proc. 2009 VLSI Design/CAD Symposium, Hua-Lien, Taiwan, August 4-7, 2009.

Cheng-An Chien, Yao-Chang Yang, Jia-Wei Chen, Hsiu-Cheng Chang, Chin-Hsien Wang, Hsiang-Hui Huang, Ching-Hwa Cheng, Jinn-Shan Wang, and Jiun-In Guo,” A 439K Gates/10.9KB SRAM/2-328 mW Dual Mode Video Decoder Supporting Temporal/Spatial Scalable Video,” Proc. 2009 VLSI Design/CAD Symposium, Hua-Lien, Taiwan, August 4-7, 2009.

Cheng-An Chien, Yao-Chang Yang, Jia-Wei Chen, Hsiu-Cheng Chang, Chin-Hsien Wang, Hsiang-Hui Huang, Ching-Hwa Cheng, Jinn-Shan Wang, and Jiun-In Guo,” A 439K Gates/10.9KB SRAM/2-328 mW Dual Mode Video Decoder Supporting Temporal/Spatial Scalable Video,” Proc. 2009 IEEE Asian Solid-State Circuits Conference (ASSCC), Taipei, Taiwan, November 16-18, 2009.

Guo-An Jian, Jui-Chin Chu, and Jiun-In Guo,” Optimization of AVS-M Video Decoder for Real-time Implementation on Embedded RISC Processors,” Proc. of the Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIHMSP-2009), Kyoto, Japan, September 12-14, 2009.

Cheng-An Chien, Hsiu-Cheng Chang, and Jiun-In Guo,” A High Throughput Deblocking Filter Design Supporting Multiple Video Coding Standards,” Proc. 2009 IEEE International Symposium on Circuits and Systems, May 24-27, Taipei, Taiwan, 2009.

Guo-An Jian, Jui-Chin Chu, Ting-Yu Huang, Tao-Cheng Chang, and Jiun-In Guo,” A System Architecture Exploration on the Configurable HW/SW Co-Design for H.264 Video Decoder,” Proc. 2009 IEEE International Symposium on Circuits and Systems, May 24-27, Taipei, Taiwan, 2009.

Hsiu-Cheng Chang, Yao-Chang Yang, Jia-Wei Chen, Ching-Lung Su, Cheng-An Chien, Jiun-In Guo, and Jinn-Shyan Wang,” A Dynamic Quality-Scalable H.264 Video Encoder Chip,” Proc. IEEE 14th Asia and South Pacific Design Automation Conference (ASP-DAC2009), Jan. 19~22, Yokohama, Japan, 2009.

Chin-Hsien Wang, Ching-Hwa Cheng, and Jiun-In Guo,” CKVdd: A Self-Stabilization Ramp-Vdd Technique for Dynamic Power Reduction,” Proc. IEEE 14th Asia and South Pacific Design Automation Conference (ASP-DAC2009), Jan. 19~22, Yokohama, Japan, 2009.

Guo-An Jian, Ting-Yu Huang, Jui-Chin Chu, and Jiun-In Guo, “Optimization of VC-1/H.264/AVS Video Decoders on Embedded Processors,” Proc. 6^th International Conference on Information Technology: New Generations, April 27-29, Las Vegas, Nevada, USA, 2009.

Jui-Chin Chu, Liang-Fei Su, Yao-Chang Yang, Ching-Lung Su, and Jiun-In Guo,” A Multi-mode Entropy Decoder with a Generic Table Partition Strategy,” Proc. 2008 IEEE International SoC Design Conference, Nov. 24-Nov.25, Busan, Korea, 2008.

Bing-Tsung Wu, Tzu-Chun Chang, Jiun-In Guo, and Ching-Lung Su,” A Novel Basic Unit Level Rate Control Algorithm and Architecture for H.264/AVC Video Encoders,” Proc. 2008 IEEE Asia Pacific Conference on Circuits and Systems, Macao, China, Nov 30 - Dec 3, 2008.

Cheng-An Chien, Hsiu-Cheng Chang, and Jiun-In Guo, “A High Throughput In-Loop De-blocking Filter Supporting H.264/AVC BP/MP/HP Video Coding,” Proc. 2008 IEEE Asia Pacific Conference on Circuits and Systems, Macao, China, Nov 30 - Dec 3, 2008.

Ping-Tsung Wu, Tzu-Chun Chang, Ching-Lung Su, Jiun-In Guo, “A H.264 Basic-Unit Level Rate Control Algorithm Facilitating Hardware Realization,” Proc. 2008 IEEE International Conference on Acoustics, Speech, and Signal Processing, March 31~April 4, Las Vegas, Nevada, USA, 2008.

Ting-Yu Huang, Guo-An Jian, Jui-Chin Chu, Ching-Lung Su, and Jiun-In Guo, “Joint Algorithm/Code-level Optimization of H.264 Video Decoder for Mobile Multimedia Applications,” Proc. 2008 IEEE International Conference on Acoustics, Speech, and Signal Processing, March 31~April 4, Las Vegas, Nevada, USA, 2008.

Chun-Hao Chang, Jia-Wei Chen, Hsiu-Cheng Chang, Yao-Chang Yang, Jinn-Shyan Wang, Jiun-In Guo, “A Quality Scalable H.264/AVC Baseline Intra Encoder for High Definition Video Applications” Proc. 2007 IEEE Workshop on Signal Processing Systems, Oct. 17-19, Shanghai, China 2007.

Guo-An Jian, and Jiun-In Guo, “A Low Complexity Multi-standard Video Player for Portable multimedia Applications,” Proc. 2007 IEEE International Conference on Multimedia & Expo, July 2-5, Beijing, China 2007.

Chih-Da Chien, Chih-Wei Wang, Chuan-Chau Lin, Tien-Wei Hsieh, Yuan-Hwa Chu, and Jiun-In Guo, “A Low Latency Memory Controller for Video Coding Systems,” Proc. 2007 IEEE International Conference on Multimedia & Expo, July 2-5, Beijing, China 2007.

Jui-Chin Chu, Wei-Chun Ku, Shu-Hsuan Chou, Tien-Fu Chen, and Jiun-In Guo, “An Embedded Coherent-Multithreading Multimedia Processor and Its Programming Model”, Proc. 44^th Design Automation Conference (DAC), June, 2007.

Kuan-Hung Chen, Yuan-Sun Chu, Yu-Min Chen, and Jiun-In Guo, “A High-Speed/Low-Power Multiplier Using an Advanced Spurious Power Suppression Technique,” Proc. 2007 IEEE International Symposium on Circuits and Systems, May 27-May 30, New Orleans, USA, 2007.

Guo-An Jian, Chih-Da Chien, and Jiun-In Guo, “A Memory-Based Hardware Accelerator for Real-Time MPEG-4 Audio Coding and Reverberation,” Proc. 2007 IEEE International Symposium on Circuits and Systems, May 27-May 30, New Orleans, USA, 2007.

Hsiu-Cheng Chang, Jia-Wei Chen, Ching-Lung Su, Yao-Chang Yang, Yao Li, Chun-Hao Chang, Ze-Min Chen, Wei-Sen Yang, Chien-Chang Lin, Ching-Wen Chen, Jinn-Shan Wang, and Jiun-In Guo, “A 7mW~183mW Dynamic Quality-Scalable H.264 Video Encoder Chip,” Proc. 2007 IEEE International Solid-State Circuits Conference, Feb. 2007.

Chih-Da Chien, Chien-Chang Lin, Yi-Hung Shih, He-Chun Chen, Chia-Jui Huang, Cheng-Yen Yu, Chih-Liang Chen, Ching-Hwa Cheng, and Jiun-In Guo^, “A 252K Gates/71mW Multi-Standard Multi-Channel Video Decoder for High Definition Video Applications,” Proc. 2007 IEEE International Solid-State Circuits Conference, Feb. 2007.

Kuan-Hung Chen, Yu-Min Chen, Yuan-Sun Chu, and Jiun-In Guo, “A Versatile Multimedia Functional Unit Design Using the Spurious Power Suppression Technique, “Proc. 2006 IEEE Asia Solid-State Circuits Conference (ASSCC2006), Hangzhou, China, Nov. 13-15, 2006.

Min-Shuan Lee, Jui-Chin Chu, and Jiun-In Guo, “Predictive Mode Searching Policy for H.264/AVC Intra Prediction, “Proc. 2006 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS 2006), Singapore, December 4-7, 2006.

Ching-Lung Su, Yao Li, Ching-Wen Chen, Wei-Sen Yang, Ya-Li Chen, S-Y Tseng, and Jiun-In Guo, “Low Complexity High Quality Fractional Motion Estimation Algorithm and Architecture Design for H.264/AVC, “Proc. 2006 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS 2006), Singapore, December 4-7, 2006.

Ching-Lung Su, Yao-Chang Yang, Ching-Wen Chen, Wei-Sen Yang, Ya-Li Chen, S-Y Tseng, and Jiun-In Guo, “A Low Complexity High Quality Interger Motion Estimation Architecture Design for H.264/AVC, “ Proc. 2006 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS 2006), Singapore, December 4-7, 2006.

Wei-Chun Ku, Shu-Hsuan Chou, Jui-Chin Chu, Chih-Heng Kang, Tien-Fu Chen, Jiun-In Guo, “Cooperative Multithreading: An Open Scalable and Configurable Processor for Embedded Multimedia Applications,” Proc. 2006 IEEE International Conference on Multimedia & Expo, July 9-12, Toronto, Ontario, Canada, 2006.

Jia-Wei Chen, Chun-Hao Chang, Chien-Chang Lin, Yi-Huan Ou Yang, Jiun-In Guo, and Jinn-Shyan Wang, “A Condition-based Intra Prediction Algorithm for H.264/AVC,” Proc. 2006 IEEE International Conference on Multimedia & Expo, July 9-12, Toronto, Ontario, Canada, 2006.

Yao-Chang Yang, Chien-Chang Lin, Hsui-Cheng Chang, Ching-Lung Su, and Jiun-In Guo, “A High Throughput VLSI Architecture Design for H.264 Context-Based Adaptive Binary Decoding with Look Ahead Parsing,” Proc. 2006 IEEE International Conference on Multimedia & Expo, July 9-12, Toronto, Ontario, Canada, 2006.

Jia-Wei Chen, Chien-Chang Lin, Jiun-In Guo, Jinn-Shyan Wang, “Low Complexity Architecture Design of H.264 Predictive Pixel Compensator for HDTV Applications, “Proc. 2006 IEEE International Conference on Acoustics, Speech, and Signal Processing, May 14-19, Toulouse, France, 2006.

Kuo-Chuan Chao, Kuan-Hung Chen, Yuan-San Chu, and Jiun-In Guo, “Low-power mechanism with power block management,” Proc. 2006 IEEE International Symposium on Circuits and Systems, May 21-May 24, Island of Kos, Greece, 2006.

Jui-Chin Chu, Chih-Wen Huang, He-Chun Chen, Keng-Po Lu, Ming-Shuan Lee, Jiun-In Guo, and Tien-Fu Chen, “Design of Customized Functional Units for the VLIW-based Multi-threading Processor Core Targeted at Multimedia Applications,” Proc. 2006 IEEE International Symposium on Circuits and Systems, May 21-May 24, Island of Kos, Greece, 2006.

Chih-Da Chien, Keng-Po Lu, Yi-Hung Shih, and Jiun-In Guo, “A High Performance CAVLC Encoder Design for MPEG-4 AVC/H.264 Video Coding Applications,” Proc. 2006 IEEE International Symposium on Circuits and Systems, May 21-May 24, Island of Kos, Greece, 2006.

Jia-Wei Chen, Kuan-Hung Chen, Jiun-In Guo, and Jinn-Shyan Wang, “A Performance-Aware IP Core Design for Multi-mode Transform Coding Using Scalable-DA Algorithm,” Proc. 2006 IEEE International Symposium on Circuits and Systems, May 21-May 24, Island of Kos, Greece, 2006.

C. C. Lin, J. I. Guo, H. C. Chang, Y. C. Yang, J. W. Chen, M. C. Tsai, and J. S. Wang, “A 160kGates 4.5KB SRAM H.264 Video Decoder for HDTV Applications,” 2006 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, Session 22.3, pages 9-11, Feb. 2006.

Kuan-Hung Chen, Kuo-Chuan Chao, Jinn-Shyan Wang, Yuan-Sun Chu, and Jiun-In Guo, “Design Exploration of a Spurious Power Suppression Technique (SPST) and Its Applications,” Proc. 2005 IEEE Asian Solid State Circuits Conference (ASSCC’2005), Nov. 1~3, Hsinchu, Taiwan, R.O.C.

Kuan-Hung Chen, Kuo-Chuan Chao, Jiun-In Guo, Jinn-Shyan Wang, and Yuan-Sun Chu, “An Efficient Spurious Power Suppression Technique (SPST) and its Applications on MPEG-4 AVC/H.264 Transform Coding Design,” Proc. 2005 International Symposium on Low Power Electronics and Design, ISLPED’2005, August 8-10, San-Diego, California, USA.

Kuan-Hung Chen, Jiun-In Guo, Kuo-Chuan Chao, Jinn-Shyan Wang, and Yuan-Sun Chu, “High-Performance Low Power Direct 2-D Transform Coding IP Design for MPEG-4 AVC/H.264 with switching power suppression technique,” Proc. 2005 IEEE VLSI-TSA, International Symposium on VLSI Design, Automation & Test (VLSI-DAT), April 27-29, Hsinchu, Taiwan, R.O.C. 2005.

Chih-Da Chien, Ho-Chun Chen, Lin-Chieh Huang, and Jiun-In Guo, “A Low-Power Motion Compensation IP Core Design for MPEG-1/2/4 Video Decoding,” Proc. 2005 IEEE International Symposium on Circuits and Systems, May 23-May 26, Kobe, Japan, 2005.

Kuan-Hung Chen, Jiun-In Guo, and Jinn-Shyan Wang, “High-Performance Direct 2-D Transform Coding IP Design for MPEG-4 AVC/H.264,” Proc. 2005 IEEE International Symposium on Circuits and Systems, May 23-May 26, Kobe, Japan, 2005.

Hsiu-Cheng Chang, Chien-Chang Lin, and Jiun-In Guo, “A Novel Low-Cost High-Performance VLSI Architecture for MEPG AVC/H.264 CAVLC Decoding,” Proc. 2005 IEEE International Symposium on Circuits and Systems, May 23-May 26, Kobe, Japan, 2005.

Hsiu-Cheng Chang, Chien-Chang Lin, Ming-Chih Tsai, Kuan-Hung Chen, and Jiun-In Guo, “Parameterized Multi-MPEG Texture Decoder IP Design,” Proc. 2004 VLSI DESIGN/CAD Symposium, Aug. 10-13, Taiwan, R.O.C, 2004.

Tai-Lun Chang, Ying-Ming Tsai, Hsiu-Cheng Chang, Chih-Da Chien, and Jiun-In Guo,” A High-Performance Reconfigurable Multi-MPEG Bitstream Processing IP Core,” Proc. 2004 VLSI DESIGN/CAD Symposium, Aug. 10-13, Taiwan, R.O.C, 2004.

Chien-Chang Lin, Hsiu-Cheng Chang, Kuan-Hung Chen, and Jiun-In Guo, “Reconfigurable Low Power MPEG-4 Texture Decoder IP Design,” Proc. 2004 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS 2004), Tainan, Taiwan, December 6-9, 2004.

Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, and Ching-Wei Yeh, “A Power-Aware SNR-Progressive DCT/IDCT IP Core Design for Multimedia Transform Coding,” Proc. 2004 IEEE International Conference on Multimedia & Expo, June 27-30, Taipei, Taiwan, 2004.

Tai-Lun Chang, Ying-Ming Tsai, Chih-Da Chien, Chien-Chang Lin, and Jiun-In Guo, “A HIGH-PERFORMANCE MPEG4 BITSTREAM PROCESSING CORE,” Proc. 2004 IEEE International Conference on Multimedia & Expo, June 27-30, Taipei, Taiwan, 2004.

Hun-Chen Chen, Jui-Cheng Yen, Jiun-In Guo and Chi-Shiung Lin, “Design and Implementation of a K-Winners-Take-All Neural Network,” Proc. 2004 IEEE International Symposium on Nanoelectronic Circuits and Gigascale Systems (ISNCGS2004), Feb. 12-13, Miao-Li, Taiwan, 2004.

Tai-Lun Chang, Ying-Ming Tsai, Chih-Da Chien, Chien-Chang Lin, and Jiun-In Guo, “A HIGH-PERFORMANCE BITSTREAM PROCESSING IP CORE DESIGN FOR MPEG4 VIDEO COMPRESSION APPLICATIONS,” Proc. 2004 IEEE International Symposium on Nanoelectronic Circuits and Gigascale Systems (ISNCGS2004), Feb. 12-13, Miao-Li, Taiwan, 2004.

Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, and Ching-Wei Yeh, “A DCT/IDCT IP Core Design for Multimedia Transform Coding,” Proc. 2004 IEEE International Symposium on Nanoelectronic Circuits and Gigascale Systems (ISNCGS2004), Feb. 12-13, Miao-Li, Taiwan, 2004.

Chih-Da Chien, Chien-Chang Lin, and Jiun-In Guo,“A PARAMETERIZED IP CORE GENERATOR FOR THE ONE-DIMENSIONAL LONG-LENGTH DISCRETE FOURIER TRANSFORM,” Proc. 2004 IEEE International Symposium on Nanoelectronic Circuits and Gigascale Systems (ISNCGS2004), Feb. 12-13, Miao-Li, Taiwan, 2004.

Chih-Da Chien, Chien-Chang Lin, Jiun-In Guo, and Tien-Fu Chen, “A POWER- AWARE IP CORE GENERATOR FOR THE ONE-DIMENSIONAL DISCRETE FOURIER TRANSFORM,” Proc. 2004 IEEE International Symposium on Circuits and Systems, May 23-May 26, Vancouver, Canada, 2004.

Rei-Chin Ju, Jia-Wei Chen, Jiun-In Guo, and Tien-Fu Chen, “A PARAMETERIZED POWER-AWARE IP CORE GENERATOR FOR THE 2-D 8x8 DCT/IDCT, “ Proc. 2004 IEEE International Symposium on Circuits and Systems, May 23-May 26, Vancouver, Canada, 2004.

Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, and Tien-Fu Chen, “A POWER-AWARE IP CORE DESIGN FOR THE VARIABLE-LENGTH DCT/IDCT TARGETING AT MPEG4 SHAPE-ADAPTIVE TRANSFORMS,” Proc. 2004 IEEE International Symposium on Circuits and Systems, May 23-May 26, Vancouver, Canada, 2004.

Hun-Chen Chen, Lin-Chieh Huang, Jui-Cheng Yen, and J. I. Guo, “DESIGN AND IMPLEMENTATION OF A NEW CHAOTIC SIGNAL SECURITY SYSTEM FOR MULTIMEDIA APPLICATIONS,” Proc. 2003 VLSI DESIGN/CAD Symposium, Aug. 12-15, Taiwan, R.O.C, 2003.

W. C. Lee, C. M. Liu, C. H. Yang, and J. I. Guo, “Fast Perceptual Convolution for the Room Reverberation”, Proc. of the 6^th International Conference on Digital Audio Effects (DAFX-03), Queen Mary, University of London, September 8-11, 2003.

W. C. Lee, C. H. Yang, C. M. Liu and J. I. Guo, “Perceptual Convolution for Reverberation”, Proc. of 115^th AES Convention, Oct. 10-13, Jacob K. Javits Convention Center, New York, USA, 2003.

Hun-Chen Chen, J. I. Guo, and Chien-Wei Jen, “A Memory Efficient Realization of Cyclic Convolution and its Application to Discrete Cosine Transform,” Proc. 2003 IEEE International Symposium on Circuits and Systems, May 25-May 28, Bangkok, Thailand, 2003.

J. I. Guo, Chih-Da Chien, and, Chien-Chang Lin, “A Parameterized Low Power Design for the Variable-Length Discrete FOURIER Transform using Dynamic Pipelining,” Proc. 2003 IEEE International Symposium on Circuits and Systems, May 25-May 28, Bangkok, Thailand, 2003.

J. I. Guo, Jia-Wei Chen, and Han-Chen Chen, “A New 2-D 8x8 DCT/IDCT Core Design using Group Distributed Arithmetic,” Proc. 2003 IEEE International Symposium on Circuits and Systems, May 25-May 28, Bangkok, Thailand, 2003.

J. I. Guo, Chiun-Chau Lin, Min-Chih Tsai, and Sheng-Wei Lin, “An Efficient Voice over Internet Protocol Technique Combining the Speech Data Encryption and G.729 Error Recovery,” Proc. 2002 International Computer Symposium (ICS2002), Dec. 18~21, Taiwan, R.O.C.

J. I. Guo, Chien-Chang Lin, and Chih-Da Chien, “A Low Power Parameterized Hardware Design for the One Dimensional Discrete FOURIER Transform,” Proc. 2002 IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2002), pp. 407-411, Nov. 21~24, Taiwan, R.O.C.

Hun-Chen Chen, Jui-Cheng Yen, and J. I. Guo, “Design of a New Cryptography System,” Proc. 2002 The Third IEEE Pacific-Rim Conference on Multimedia (PCM2002), Dec. 16~18, Taiwan, R.O.C.

H. C. Chen, and J. I. Guo, “A New Group Distributed Arithmetic Approach and Hardware Design for One Dimensional Discrete Hartley Transform,” Proc. 2002 VLSI DESIGN/CAD Symposium, Aug. 12-15, 2002, Taiwan, R.O.C.

Rei-Chin Ju, Li-Tin Yeh, and J. I. Guo, “A Low Power Parameterized Hardware Core Design for the Discrete Cosine and Sine Transforms,” Proc. 2002 VLSI DESIGN/CAD Symposium, Aug. 12-15, 2002, Taiwan, R.O.C.

Chien-Chang Lin, Chih-Da Chien, and J. I. Guo, “A Parameterized Hardware Design for the Variable Length Discrete Fourier Transform,” Proc. 2002 VLSI DESIGN/CAD Symposium, Aug. 12-15, 2002, Taiwan, R.O.C.

J. I. Guo and Chien-Chang Lin, “A New Hardware Efficient Design for the One Dimensional Discrete Fourier Transform,” Proc. 2002 IEEE International Symposium on Circuits and Systems, pp. V-549~V-552, May 26-May 29, Scottsdale, Arizona, U.S.A, 2002.

H. C. Chen, J. I. Guo, and C. W. Jen, “A New Group Distributed Arithmetic Design for the One Dimensional Discrete Fourier Transform,” Proc. 2002 IEEE International Symposium on Circuits and Systems, pp. I-421~I-424, May 26-May 29, Scottsdale, Arizona, U.S.A, 2002.

Jui-Cheng Yen and J. I. Guo,” Design of a New Signal Security System,” Proc. 2002 IEEE International Symposium on Circuits and Systems, pp. IV-121~IV-124, May 26-May 29, Scottsdale, Arizona, U.S.A, 2002.

J. I. Guo, Jui-Cheng Yen, and Jo-Yo Lin, “The FPGA Realization of a New Image Encryption/Decryption Design,” Proc. 2001 VLSI DESIGN/CAD Symposium, Aug. 15-17, 2001.

J. I. Guo, Jia-Wei Chen, and Cheng-Chung Wu, “An Efficient Adder-Based 2-D DCT/IDCT Design for Image Compression Applications,” Proc. 2001 VLSI DESIGN/CAD Symposium, Aug. 15-17, 2001.

J. I. Guo, “A New DA-Based Array for One Dimensional Discrete Hartley Transform, “ Proc. 2001 IEEE International Symposium on Circuits and Systems, pp.IV-662~IV-665, May 6-9, Sydney, Australia, 2001.

J. I. Guo, “A Low Cost 2-D Inverse Discrete Cosine Transform design for Image Compression,” Proc. 2001 IEEE International Symposium on Circuits and Systems, pp. IV-658~IV-661, May 6-9, Sydney, Australia, 2001.

C. C. Li, and J. I. Guo, “A General Design for the One Dimensional Discrete Cosine and Sine Transforms,” Proc. 2000 National Symposium on Telecommunications, pp.1-320~1-325, Dec. 15-16, Chun-Li, Taiwan, R.O.C.

J. I. Guo, J. C. Yen, and S. F. Pai, “An Internet Telephony System Design with Hierarchical Data Security Protection,” Proc. 2000 WORKSHOP on Consumer Electronics: Digital Video, 3C and Information Appliance, pp. 56-61, Oct.19-20, Taipei, Taiwan, R.O.C.

Jui-Cheng Yen and J. I. Guo, “A New Chaotic Key-Based Design for Image Encryption and Decryption,” Proc. 2000 IEEE International Symposium on Circuits and Systems, pp. IV-49~IV-52, May 28-31, GENEVA, SWITZERLAND, 2000.

J. I. Guo, “An Efficient Design for One Dimensional Discrete Cosine Transform Using Parallel Adders,” Proc. 2000 IEEE International Symposium on Circuits and Systems, pp. V-725~V.728, May 28-31, GENEVA, SWITZERLAND, 2000.

Jui-Cheng Yen and J. I. Guo, “A New Neural MPEG/Encryption System”, Proc. 1999 WORKSHOP on Consumer Electronics: Digital Video and Multimedia Communications, pp.119-122, Oct. 18-19, Taipei, Taiwan, R.O.C.

Jui-Cheng Yen and J. I. Guo, “A new MPEG/encryption system and its VLSI architecture,” Proc. 1999 International Symposium on Communications, pp.215-219, Nov. 7-10, 1999.

Jiun-In Guo, Jui-Cheng Yen, and Jen-Chieh Yeh, “The design and realization of a new hierarchical Chaotic image encryption algorithm”, Proc. 1999 International Symposium on Communications, pp. 210-214, Nov. 7-10, 1999.

Hun-Chen Chen, Jiun-In Guo and Chein-Wei Jen, “LOW POWER MODULE DESIGNS FOR VIDEO CODEC SYSTEMS,” Proc. 1999 Tenth VLSI DESIGN/CAD Symposium, pp.275-278, Aug. 18-21, 1999.

Jui-Cheng Yen and J. I. Guo, “A Chaotic Neural Network for Signal Encryption/Decryption and Its VLSI Architecture,” Proc. 1999 Tenth VLSI DESIGN/CAD Symposium, pp.319-322, Aug. 18-21, 1999.

J. I. Guo and Jui-Cheng Yen, “A New Mirror-Like Image Encryption Algorithm and Its VLSI Architecture,” Proc. 1999 Tenth VLSI DESIGN/CAD Symposium, pp.327-330, Aug. 18-21, 1999.

J. I. Guo, “An Efficient Parallel Adder Based Design for the One Dimensional Discrete Hartley Transform,” Proc. 1999 Tenth VLSI DESIGN/CAD Symposium, pp.247-250, Aug. 18-21, 1999.

Jui-Cheng Yen and J. I. Guo, “A New Image Encryption Algorithm and Its VLSI Architecture,” Proc. 1999 IEEE Workshop on SiGNAL PROCESSING SYSTEMS (SiPS) Design and implementation, pp.430-437, Oct. 20-22, Taipei, Taiwan, R.O.C.

T. S. Chang, J. I. Guo, and C. W. Jen, “A Compact IDCT Processor for HDTV Applications,” Proc. 1999 IEEE Workshop on SiGNAL PROCESSING SYSTEMS (SiPS) Design and implementation, pp.151-158, Oct. 20-22, Taipei, Taiwan, R.O.C.

J. I. Guo, “The Design of Memory-based VLSI Array for One-Dimensional Discrete Hartley Transform,” Proc. 1998 National Symposium on Telecommunications, pp.63-68, Dec. 18-19, 1998.

Jui-Cheng Yen and J. I. Guo, “A New Chaotic Image Encryption Algorithm,” Proc. 1998 National Symposium on Telecommunications, pp.358-362, Dec. 18-19, 1998.

Jui-Cheng Yen and J. I. Guo, “A New Hierarchical Chaotic Image Encryption Algorithm and Its Hardware Architecture,” Proc. 1998 Nineth VLSI DESIGN/CAD Symposium, Aug. 19-22, 1998.

J. I. Guo and C. W. Jen, "A systolic algorithm and architecture for the fast cosine transform," Proc. National Computer Symposium 1995 Republic of China, vol.1, pp.98-105, Dec. 1995.

J. I. Guo, C. M. Liu, and C. W. Jen, "A VLSI Array Design for Discrete Fourier Transform Using Distributed Arithmetic," Proc. 1995 ROC Tenth Technical Education Conference, pp.359-368, May 1995.

J. I. Guo, C. M. Liu, and C. W. Jen, "A general memory-based approach to design efficient VLSI arrays for the multi-dimensional discrete Hartley transform," Proc. 1994 IEEE International Symposium on Circuits and Systems, May 30 - June 2, 1994.

J. I. Guo, C. M. Liu, and C. W. Jen, "A novel VLSI array design for the discrete Hartley transform using cyclic convolution," Proc. 1994 IEEE International Conference on Acoustics, Speech, and Signal Processing, April 19-22, 1994.

Y. S. Lin, J. I. Guo, and C. W. Jen, "A multi-phase shared bus structure for fast Fourier transform," Proc. 1993 IEEE International Symposium on Circuits and Systems, May 3-6, pp.1575-1578, 1993.

J. I. Guo, C. M. Liu, and C. W. Jen, "A CORDIC-based VLSI array for computing 2-D discrete Hartley transform," Proc. 1993 IEEE International Symposium on Circuits and Systems, May 3-6, pp.1571-1574, 1993.

J. I. Guo, C. M. Liu, and C. W. Jen, "A memory-based systolic array chip for the 1-D discrete cosine transform," Proc. 1993 Fourth VLSI DESIGN/CAD Workshop, pp.96-100, Aug. 26-28, 1993.

J. I. Guo, C. M. Liu, and C. W. Jen, "A two-level pipelined systolic array chip for computing the discrete cosine transform," Proc. 1993 International Symposium on VLSI Technology, Systems, and Applications, May 12-14, pp.199-203, 1993.

J. I. Guo, C. M. Liu, and C. W. Jen, "A memory-based approach to design and implement systolic arrays for DFT and DCT," Proc. 1992 IEEE International Conference on Acoustics, Speech, and Signal Processing, vol.5, pp. V-621~V-624, 1992.

J. I. Guo, C. M. Liu, and C. W. Jen, "New systolic arrays for prime length discrete cosine transform," Proc. IEEE Workshop on Visual Signal Processing and Communications, Hsinchu, Taiwan, R.O.C., pp.67-70, June, 1991.

林勝尉、黃銘卿、郭峻因, “影像壓縮及資料加/解密技術在遠端監控系統上的發展與應用,” 機電整合 Mechatronics Magazine, pp.132-137, June 2004.

郭峻因, “應用於數位訊號處理之可參數化數位矽智財產生器設計,”國科會工程科技通訊七十四期電機類, 2004.

陳冠宏、林建璋、朱瑞欽、簡志達、郭峻因, “Overview on MPEG-4 Video CODEC System Design,” 影像與識別 Image & Recognition Magazine, vol. 10, no. 1, pp. 54-101, March 2004.